All Releases by Vikas Naresh Kumar

River gauge Release Uploaded
River stage one • 1 direct dependent • 1 total dependent PDL-Finance-TA-0.03 PDL::Finance::TA is a Technical Analysis GUI 16 Aug 2014 15:44:12 UTC
River stage one • 1 direct dependent • 1 total dependent PDL-Finance-TA-0.02 PDL::Finance::TA is a Technical Analysis GUI 16 Aug 2014 15:15:56 UTC
River stage zero No dependents Module-Build-Xilinx-0.13 Xilinx ISE Webpack based FPGA Development using commandline 28 Jul 2014 19:17:51 UTC
River stage zero No dependents Module-Build-Xilinx-0.12 Xilinx ISE Webpack based FPGA Development using commandline 17 Jul 2014 13:57:02 UTC
River stage zero No dependents Module-Build-Xilinx-0.11 Xilinx ISE Webpack based FPGA Development using commandline 16 Jul 2014 20:56:36 UTC
River stage zero No dependents Module-Build-Xilinx-0.10 Xilinx ISE Webpack based FPGA Development using commandline 14 Jul 2014 23:05:18 UTC
River stage zero No dependents Module-Build-Xilinx-0.09 Xilinx ISE Webpack based FPGA Development using commandline 14 Jul 2014 22:52:13 UTC
River stage zero No dependents Module-Build-Xilinx-0.08 Xilinx ISE Webpack based FPGA Development using commandline 11 Jul 2014 16:37:48 UTC
River stage zero No dependents Module-Build-Xilinx-0.07 Xilinx ISE Webpack based FPGA Development using commandline 11 Jul 2014 15:04:26 UTC
River stage zero No dependents Module-Build-Xilinx-0.06 Xilinx ISE Webpack based FPGA Development using commandline 09 Jul 2014 14:43:14 UTC
River stage zero No dependents Module-Build-Xilinx-0.05 Xilinx ISE Webpack based FPGA Development using commandline 08 Jul 2014 14:27:59 UTC
River stage zero No dependents Module-Build-Xilinx-0.04 Module::Build::Xilinx generates Tcl scripts to create and build Xilinx ISE projects and can compile VHDL files present in the lib/ directory. 07 Jul 2014 17:18:39 UTC
River stage zero No dependents Module-Build-Xilinx-0.03 Module::Build::Xilinx generates Tcl scripts to create and build Xilinx ISE projects and can compile VHDL files present in the lib/ directory. 07 Jul 2014 16:44:09 UTC
River stage zero No dependents Module-Build-Xilinx-0.02 Module::Build::Xilinx generates Tcl scripts to create and build Xilinx ISE projects and can compile VHDL files present in the lib/ directory. 03 Jul 2014 13:19:00 UTC
River stage zero No dependents VIC-0.11 VIC is a high level syntax to generate PIC microcontroller assembly 03 Jul 2014 03:02:27 UTC
River stage zero No dependents VIC-0.10 VIC is a high level syntax to generate PIC microcontroller assembly 02 Jul 2014 03:51:03 UTC
River stage zero No dependents Module-Build-Xilinx-0.01 Module::Build::Xilinx generates Tcl scripts to create and build Xilinx ISE projects and can compile VHDL files present in the lib/ directory. 02 Jul 2014 03:49:36 UTC
River stage zero No dependents Device-SaleaeLogic-0.02 Perl extension for accessing the Logic or Logic16 devices made by Saleae Logic. 13 Jun 2014 15:01:35 UTC
River stage zero No dependents Device-SaleaeLogic-0.01 Perl extension for blah blah blah 12 Jun 2014 21:11:38 UTC
No river data available Alien-SaleaeLogic-0.01 Easy installation of the Saleae Logic SDK 02 Jun 2014 19:16:32 UTC
River stage one • 1 direct dependent • 2 total dependents Alien-TALib-0.04 Alien module for ta-lib from http://ta-lib.org 30 May 2014 22:44:23 UTC
River stage zero No dependents VIC-0.09 VIC is a high level syntax to generate PIC microcontroller assembly 19 May 2014 13:16:45 UTC
River stage zero No dependents VIC-0.08 VIC is a high level syntax to generate PIC microcontroller assembly 19 May 2014 12:50:38 UTC
River stage zero No dependents VIC-0.07 VIC is a high level syntax to generate PIC microcontroller assembly 07 May 2014 20:38:40 UTC
River stage zero No dependents VIC-0.06 VIC is a high level syntax to generate PIC microcontroller assembly 22 Apr 2014 02:27:24 UTC
River stage zero No dependents VIC-0.05 VIC is a high level syntax to generate PIC microcontroller assembly 09 Apr 2014 23:22:14 UTC
River stage zero No dependents VIC-0.04 VIC is a high level syntax to generate PIC microcontroller assembly 28 Mar 2014 13:56:28 UTC
River stage zero No dependents VIC-0.03 VIC is a high level syntax to generate PIC microcontroller assembly 26 Feb 2014 11:28:33 UTC
River stage zero No dependents VIC-0.02 VIC is a high level syntax to generate PIC microcontroller assembly 15 Feb 2014 21:29:22 UTC
River stage zero No dependents VIC-0.01 VIC is a high level syntax to generate PIC microcontroller assembly 14 Feb 2014 16:26:56 UTC
No river data available Finance-SEC-Edgar-0.01 Finance::SEC::Edgar provides downloads of SEC EDGAR filings 21 Jan 2014 14:53:47 UTC
River stage one • 1 direct dependent • 2 total dependents Alien-TALib-0.031 Alien module for ta-lib from http://ta-lib.org 13 Jan 2014 14:10:32 UTC
River stage one • 1 direct dependent • 2 total dependents Alien-TALib-0.03 Alien module for ta-lib from http://ta-lib.org 12 Jan 2014 23:17:42 UTC
River stage one • 1 direct dependent • 2 total dependents Alien-TALib-0.02 Alien module for ta-lib from http://ta-lib.org 12 Jan 2014 17:32:47 UTC
River stage one • 1 direct dependent • 1 total dependent PDL-Finance-TA-0.01 PDL::Finance::TA provides technical analysis functions for PDL 04 Jan 2014 06:40:25 UTC
River stage one • 1 direct dependent • 2 total dependents Alien-TALib-0.01 Alien module for ta-lib from http://ta-lib.org 18 Dec 2013 05:04:15 UTC
River stage zero No dependents NLP-Service-0.02 A RESTful NLP Service 15 Jun 2011 01:37:15 UTC
River stage zero No dependents NLP-Service-0.01 A RESTful NLP Service 30 May 2011 23:32:48 UTC
No river data available nlp-service-0.01 A RESTful NLP Service 30 May 2011 23:31:12 UTC
139 results