verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1
verilog/inc_def09.v:1: COMMENT: // DESCRIPTION: Verilog-Perl: Verilog Test module
verilog/inc_def09.v:1: /*CMT*/
verilog/inc_def09.v:2: COMMENT: //
verilog/inc_def09.v:2: /*CMT*/
verilog/inc_def09.v:3: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc_def09.v:3: /*CMT*/
verilog/inc_def09.v:4: COMMENT: // without warranty, 2009 by Wilson Snyder.
verilog/inc_def09.v:4: /*CMT*/
verilog/inc_def09.v:5:
verilog/inc_def09.v:6:
verilog/inc_def09.v:7:
verilog/inc_def09.v:8: COMMENT: // Definitions as speced
verilog/inc_def09.v:8: /*CMT*/
verilog/inc_def09.v:9: COMMENT: // Note there are trailing spaces, which spec doesn't show properly
verilog/inc_def09.v:9: /*CMT*/
verilog/inc_def09.v:10:
verilog/inc_def09.v:11: 'DS_initial $display("start", "msg1" , "msg2", "end");'
verilog/inc_def09.v:12: 'initial $display("start", "msg1" , "msg2" , "end");'
verilog/inc_def09.v:13: 'DS_initial $display("start", " msg1" , , "end");'
verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");'
verilog/inc_def09.v:15: 'DS_initial $display("start", , "msg2 ", "end");'
verilog/inc_def09.v:16: 'initial $display("start", , "msg2 ", "end");'
verilog/inc_def09.v:17: 'DS_initial $display("start", , , "end");'
verilog/inc_def09.v:18: 'initial $display("start", , , "end");'
verilog/inc_def09.v:19: 'DS_initial $display("start", , , "end");'
verilog/inc_def09.v:20: 'initial $display("start", , , "end");'
verilog/inc_def09.v:21: COMMENT: //`D("msg1") // ILLEGAL: only one argument
verilog/inc_def09.v:21: /*CMT*/
verilog/inc_def09.v:22: COMMENT: //`D() // ILLEGAL: only one empty argument
verilog/inc_def09.v:22: /*CMT*/
verilog/inc_def09.v:23: COMMENT: //`D(,,) // ILLEGAL: more actual than formal arguments
verilog/inc_def09.v:23: /*CMT*/
verilog/inc_def09.v:24:
verilog/inc_def09.v:25: COMMENT: // Defaults:
verilog/inc_def09.v:25: /*CMT*/
verilog/inc_def09.v:26:
verilog/inc_def09.v:27: 'DS_$display(5,,2,,3);'
verilog/inc_def09.v:28: '$display(5,,2,,3);'
verilog/inc_def09.v:29: 'DS_$display(1,,"B",,3);'
verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );'
verilog/inc_def09.v:31: 'DS_$display(5,,2,,);'
verilog/inc_def09.v:32: '$display(5,,2,,);'
verilog/inc_def09.v:33: COMMENT: //`MACRO1 ( 1 ) // ILLEGAL: b and c omitted, no default for c
verilog/inc_def09.v:33: /*CMT*/
verilog/inc_def09.v:34:
verilog/inc_def09.v:35:
verilog/inc_def09.v:36: 'DS_$display(1,,,,3);'
verilog/inc_def09.v:37: '$display(5,,,,"C");'
verilog/inc_def09.v:38: 'DS_$display(5,,2,,"C");'
verilog/inc_def09.v:39: '$display(5,,2,,"C");'
verilog/inc_def09.v:40: 'DS_$display(5,,2,,"C");'
verilog/inc_def09.v:41: '$display(5,,2,,"C");'
verilog/inc_def09.v:42:
verilog/inc_def09.v:43:
verilog/inc_def09.v:44: 'DS_$display(1,,0,,"C");'
verilog/inc_def09.v:45: '$display(1 ,,0,,"C");'
verilog/inc_def09.v:46: 'DS_$display(5,,0,,"C");'
verilog/inc_def09.v:47: '$display(5,,0,,"C");'
verilog/inc_def09.v:48: COMMENT: //`MACRO3 // ILLEGAL: parentheses required
verilog/inc_def09.v:48: /*CMT*/
verilog/inc_def09.v:49:
verilog/inc_def09.v:50:
verilog/inc_def09.v:51: 'DS_DS_b + 1 + DS_42 + a'
verilog/inc_def09.v:52: 'b + 1 + 42 + a'
verilog/inc_def09.v:53:
verilog/inc_def09.v:54: COMMENT: // Local tests
verilog/inc_def09.v:54: /*CMT*/
verilog/inc_def09.v:55:
verilog/inc_def09.v:56: DS_'"==)" "((((" () ';
verilog/inc_def09.v:57: '"==)" "((((" () ';
verilog/inc_def09.v:58:
verilog/inc_def09.v:59: COMMENT: // Also check our line counting doesn't go bad
verilog/inc_def09.v:59: /*CMT*/
verilog/inc_def09.v:62:
verilog/inc_def09.v:62:
verilog/inc_def09.v:62:
verilog/inc_def09.v:63:
verilog/inc_def09.v:64:
verilog/inc_def09.v:65:
verilog/inc_def09.v:66:
verilog/inc_def09.v:67:
verilog/inc_def09.v:68:
verilog/inc_def09.v:69:
verilog/inc_def09.v:70: DS_'(6) (eq=al) ZOT'
verilog/inc_def09.v:71: HERE-71 - Line71
verilog/inc_def09.v:72:
verilog/inc_def09.v:73: COMMENT: //======================================================================
verilog/inc_def09.v:73: /*CMT*/
verilog/inc_def09.v:74:
verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0
verilog/inc_nonl.v:1: COMMENT: // The lack of a newline on the next line is intentional
verilog/inc_nonl.v:1: /*CMT*/
verilog/inc_nonl.v:2: blah-no-newline-here>
verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2
verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc_ifdef.v:1: /*CMT*/
verilog/inc_ifdef.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc_ifdef.v:2: /*CMT*/
verilog/inc_ifdef.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/inc_ifdef.v:3: /*CMT*/
verilog/inc_ifdef.v:4:
verilog/inc_ifdef.v:5:
verilog/inc_ifdef.v:6:
verilog/inc_ifdef.v:7:
verilog/inc_ifdef.v:8:
verilog/inc_ifdef.v:9:
verilog/inc_ifdef.v:10:
verilog/inc_ifdef.v:11:
verilog/inc_ifdef.v:12: $display("1A");
verilog/inc_ifdef.v:13:
verilog/inc_ifdef.v:14:
verilog/inc_ifdef.v:15:
verilog/inc_ifdef.v:16: $display("2A");
verilog/inc_ifdef.v:17:
verilog/inc_ifdef.v:18:
verilog/inc_ifdef.v:19:
verilog/inc_ifdef.v:20:
verilog/inc_ifdef.v:21:
verilog/inc_ifdef.v:22: $display("3AELSE");
verilog/inc_ifdef.v:23:
verilog/inc_ifdef.v:24:
verilog/inc_ifdef.v:25:
verilog/inc_ifdef.v:26:
verilog/inc_ifdef.v:27:
verilog/inc_ifdef.v:28:
verilog/inc_ifdef.v:29:
verilog/inc_ifdef.v:30:
verilog/inc_ifdef.v:31:
verilog/inc_ifdef.v:32:
verilog/inc_ifdef.v:33:
verilog/inc_ifdef.v:34:
verilog/inc_ifdef.v:35:
verilog/inc_ifdef.v:36:
verilog/inc_ifdef.v:37:
verilog/inc_ifdef.v:38:
verilog/inc_ifdef.v:39:
verilog/inc_ifdef.v:40:
verilog/inc_ifdef.v:41:
verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2
verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc2.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc2.v:1: /*CMT*/
verilog/inc2.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc2.v:2: /*CMT*/
verilog/inc2.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/inc2.v:3: /*CMT*/
verilog/inc2.v:4: At file "verilog/inc2.v" line 4
verilog/inc2.v:5:
verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1
verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:2: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
inc3_a_filename_from_line_directive:2: /*CMT*/
inc3_a_filename_from_line_directive:3: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
inc3_a_filename_from_line_directive:3: /*CMT*/
inc3_a_filename_from_line_directive:4: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
inc3_a_filename_from_line_directive:4: /*CMT*/
inc3_a_filename_from_line_directive:5:
inc3_a_filename_from_line_directive:6:
inc3_a_filename_from_line_directive:7:
inc3_a_filename_from_line_directive:8:
inc3_a_filename_from_line_directive:9: COMMENT: // FOO
inc3_a_filename_from_line_directive:9: /*CMT*/
inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10
inc3_a_filename_from_line_directive:11:
inc3_a_filename_from_line_directive:12:
inc3_a_filename_from_line_directive:13: COMMENT: // guard
inc3_a_filename_from_line_directive:13: /*CMT*/
inc3_a_filename_from_line_directive:14:
inc3_a_filename_from_line_directive:15:
inc3_a_filename_from_line_directive:16:
inc3_a_filename_from_line_directive:17:
inc3_a_filename_from_line_directive:18:
inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2
verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:5:
verilog/inc2.v:6:
verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2
verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc1.v:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc1.v:1: /*CMT*/
verilog/inc1.v:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc1.v:2: /*CMT*/
verilog/inc1.v:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/inc1.v:3: /*CMT*/
verilog/inc1.v:4: text.
verilog/inc1.v:5:
verilog/inc1.v:6: COMMENT: //===========================================================================
verilog/inc1.v:6: /*CMT*/
verilog/inc1.v:7: COMMENT: // Includes
verilog/inc1.v:7: /*CMT*/
verilog/inc1.v:8:
verilog/inc1.v:9: COMMENT: //===========================================================================
verilog/inc1.v:9: /*CMT*/
verilog/inc1.v:10: COMMENT: // Defines
verilog/inc1.v:10: /*CMT*/
verilog/inc1.v:11:
verilog/inc1.v:12:
verilog/inc1.v:13:
verilog/inc1.v:14: COMMENT: // DEF_A0 set by command line
verilog/inc1.v:14: /*CMT*/
verilog/inc1.v:15: wire [3:0] q = {
verilog/inc1.v:16: 1'b1 ,
verilog/inc1.v:17: 1'b0 ,
verilog/inc1.v:18: 1'b1 ,
verilog/inc1.v:19: 1'b0
verilog/inc1.v:20: };
verilog/inc1.v:21:
verilog/inc1.v:22: text.
verilog/inc1.v:23:
verilog/inc1.v:24:
verilog/inc1.v:25: COMMENT: // but not
verilog/inc1.v:25:
verilog/inc1.v:26: COMMENT: /*this */
verilog/inc1.v:26: COMMENT: /* this too */
verilog/inc1.v:26: DS_foo /*CMT*/ bar /*CMT*/
verilog/inc1.v:27: COMMENT: /*CMT*/
verilog/inc1.v:27: DS_foobar2 /*CMT*/
verilog/inc1.v:28:
verilog/inc1.v:29:
verilog/inc1.v:29:
verilog/inc1.v:29:
verilog/inc1.v:32:
verilog/inc1.v:33:
verilog/inc1.v:33:
verilog/inc1.v:33:
verilog/inc1.v:33:
verilog/inc1.v:37:
verilog/inc1.v:38: COMMENT: /*******COMMENT*****/
verilog/inc1.v:38: /*CMT*/
verilog/inc1.v:39: DS_first part
verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0
verilog/inc1.v:39: second part
verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0
verilog/inc1.v:39: third part
verilog/inc1.v:40: DS_{
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40: a,
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40: b,
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40: c}
verilog/inc1.v:41: Line_Preproc_Check 41
verilog/inc1.v:42:
verilog/inc1.v:43: COMMENT: //===========================================================================
verilog/inc1.v:43: /*CMT*/
verilog/inc1.v:44:
verilog/inc1.v:45:
verilog/inc1.v:46:
verilog/inc1.v:47:
verilog/inc1.v:48:
verilog/inc1.v:49: DS_DS_deep DS_deep
verilog/inc1.v:50:
verilog/inc1.v:51:
verilog/inc1.v:52:
verilog/inc1.v:53: "Inside: `nosubst"
verilog/inc1.v:54: "`nosubst"
verilog/inc1.v:55:
verilog/inc1.v:56:
verilog/inc1.v:57: DS_x y LLZZ x y
verilog/inc1.v:58: DS_DS_p q LLZZ p q DS_r s LLZZ r s LLZZ DS_p q LLZZ p q DS_r s LLZZ r s
verilog/inc1.v:59:
verilog/inc1.v:60:
verilog/inc1.v:61:
verilog/inc1.v:62: DS_firstline comma","line LLZZ firstline comma","line
verilog/inc1.v:63:
verilog/inc1.v:64:
verilog/inc1.v:65: COMMENT: // Simulators disagree here; some substitute "a" others do not
verilog/inc1.v:65: DS_x y LLZZ "x" y /*CMT*/
verilog/inc1.v:66:
verilog/inc1.v:67:
verilog/inc1.v:68: DS_(a,b)(a,b)
verilog/inc1.v:69:
verilog/inc1.v:70:
verilog/inc1.v:71: $display(DS_"left side: \"right side\"")
verilog/inc1.v:72:
verilog/inc1.v:73:
verilog/inc1.v:74: DS_bar_suffix more
verilog/inc1.v:75:
verilog/inc1.v:76:
verilog/inc1.v:76:
verilog/inc1.v:78: DS_
verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0
verilog/inc1.v:78: $c("Zap(\"",bug1,"\");");;
verilog/inc1.v:79: DS_
verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0
verilog/inc1.v:79: $c("Zap(\"","bug2","\");");;
verilog/inc1.v:80:
verilog/inc1.v:81: COMMENT: /* Define inside comment: `DEEPER and `WITHTICK */
verilog/inc1.v:81: /*CMT*/
verilog/inc1.v:82: COMMENT: // More commentary: `zap(bug1); `zap("bug2");
verilog/inc1.v:82: /*CMT*/
verilog/inc1.v:83:
verilog/inc1.v:84: COMMENT: //======================================================================
verilog/inc1.v:84: /*CMT*/
verilog/inc1.v:85: COMMENT: // display passthru
verilog/inc1.v:85: /*CMT*/
verilog/inc1.v:86:
verilog/inc1.v:87:
verilog/inc1.v:88:
verilog/inc1.v:89:
verilog/inc1.v:90:
verilog/inc1.v:91: COMMENT: // Doesn't expand
verilog/inc1.v:91:
verilog/inc1.v:92:
verilog/inc1.v:93: initial begin
verilog/inc1.v:94: COMMENT: //$display(`msg( \`, \`)); // Illegal
verilog/inc1.v:94: /*CMT*/
verilog/inc1.v:95: $display(DS_"pre DS_thrupre DS_thrumid thrupost post: \"right side\"");
verilog/inc1.v:96: $display(DS_"left side: \"right side\"");
verilog/inc1.v:97: $display(DS_"left side: \"right side\"");
verilog/inc1.v:98: $display(DS_"DS_left_side: \"DS_right_side\"");
verilog/inc1.v:99: $display(DS_"DS_na: \"DS_right_side\"");
verilog/inc1.v:100: $display(DS_"prep ( midp1 DS_left_side midp2 ( outp ) ): \"DS_right_side\"");
verilog/inc1.v:101: $display(DS_"DS_na: \"DS_naDS_na\"");
verilog/inc1.v:102: COMMENT: // Results vary between simulators
verilog/inc1.v:102: $display(DS_"DS_DS_left_side DS_right_side /*CMT*/: \"DS_DS_left_side DS_right_side /*CMT*/\""); /*CMT*/
verilog/inc1.v:103: COMMENT: // Empty
verilog/inc1.v:103: $display(DS_"DS_: \"\""); /*CMT*/
verilog/inc1.v:104: $display(DS_"DS_left side: \"DS_right side\"");
verilog/inc1.v:105: $display(DS_"DS_left side: \"DS_right side\"");
verilog/inc1.v:106: $display("standalone");
verilog/inc1.v:107:
verilog/inc1.v:108: COMMENT: // Unspecified when the stringification has multiple lines
verilog/inc1.v:108: /*CMT*/
verilog/inc1.v:109:
verilog/inc1.v:109:
verilog/inc1.v:111: $display(DS_"twoline: \"DS_first second\"");
verilog/inc1.v:112: COMMENT: //$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
verilog/inc1.v:112: /*CMT*/
verilog/inc1.v:113: $write("*-* All Finished *-*\n");
verilog/inc1.v:114: $finish;
verilog/inc1.v:115: end
verilog/inc1.v:116: endmodule
verilog/inc1.v:117:
verilog/inc1.v:118: COMMENT: //======================================================================
verilog/inc1.v:118: /*CMT*/
verilog/inc1.v:119: COMMENT: // rt.cpan.org bug34429
verilog/inc1.v:119: /*CMT*/
verilog/inc1.v:120:
verilog/inc1.v:121:
verilog/inc1.v:121:
verilog/inc1.v:121:
verilog/inc1.v:121:
verilog/inc1.v:125:
verilog/inc1.v:126: module add1 ( input wire d1, output wire o1);
verilog/inc1.v:127: DS_
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: wire tmp_d1 = d1;
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: wire tmp_o1 = tmp_d1 + 1;
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: COMMENT: // expansion is OK
verilog/inc1.v:127: assign o1 = tmp_o1 ; /*CMT*/
verilog/inc1.v:128: endmodule
verilog/inc1.v:129: module add2 ( input wire d2, output wire o2);
verilog/inc1.v:130: DS_
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: wire tmp_d2 = d2;
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: wire tmp_o2 = tmp_d2 + 1;
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: COMMENT: // expansion is bad
verilog/inc1.v:130: assign o2 = tmp_o2 ; /*CMT*/
verilog/inc1.v:131: endmodule
verilog/inc1.v:132:
verilog/inc1.v:133:
verilog/inc1.v:133:
verilog/inc1.v:133:
verilog/inc1.v:133:
verilog/inc1.v:133:
verilog/inc1.v:138:
verilog/inc1.v:139: COMMENT: // parameterized macro with arguments that are macros
verilog/inc1.v:139: /*CMT*/
verilog/inc1.v:140:
verilog/inc1.v:141:
verilog/inc1.v:142:
verilog/inc1.v:143:
verilog/inc1.v:144: DS_
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144: generate for (i=0; i<(3); i=i+1) begin
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144: psl cover { DS_DS_m5k.f .ctl._ctl_mvldx_m1.d[i] & ~DS_DS_m5k.f .ctl._ctl_mvldx_m1.q[i] & !DS_DS_m5k.f .ctl._ctl_mvldx_m1.cond & (DS_(DS_DS_m5k.f .ctl.alive & DS_DS_m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144: psl cover { ~DS_DS_m5k.f .ctl._ctl_mvldx_m1.d[i] & DS_DS_m5k.f .ctl._ctl_mvldx_m1.q[i] & !DS_DS_m5k.f .ctl._ctl_mvldx_m1.cond & (DS_(DS_DS_m5k.f .ctl.alive & DS_DS_m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144: COMMENT: // ignorecmt
verilog/inc1.v:144: end endgenerate /*CMT*/
verilog/inc1.v:145:
verilog/inc1.v:146: COMMENT: //======================================================================
verilog/inc1.v:146: /*CMT*/
verilog/inc1.v:147: COMMENT: // Quotes are legal in protected blocks. Grr.
verilog/inc1.v:147: /*CMT*/
verilog/inc1.v:148: module prot();
verilog/inc1.v:149: `protected
verilog/inc1.v:150: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:151: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:152: `endprotected
verilog/inc1.v:153: endmodule
verilog/inc1.v:154:
verilog/inc1.v:155: module prot2();
verilog/inc1.v:156: `pragma protect begin_protected
verilog/inc1.v:157: `pragma protect encrypt_agent = "Whatever agent"
verilog/inc1.v:158: `pragma protect encrypt_agent_info = "1.2.3"
verilog/inc1.v:159: `pragma protect data_method = "aes128-cbc"
verilog/inc1.v:160: `pragma protect key_keyowner = "Someone"
verilog/inc1.v:161: `pragma protect key_keyname = "somekey", key_method = "rsa"
verilog/inc1.v:162: `pragma protect key_block encoding = (enctype = "base64")
verilog/inc1.v:163: wefjosdfjklajklasjkl
verilog/inc1.v:164: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059)
verilog/inc1.v:165: I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:166: #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:167: `pragma protect end_protected
verilog/inc1.v:168: `pragma reset protect
verilog/inc1.v:169: endmodule
verilog/inc1.v:170:
verilog/inc1.v:171: module prot3();
verilog/inc1.v:172: //pragma protect begin_protected
verilog/inc1.v:173: //pragma protect key_keyowner=Cadence Design Systems.
verilog/inc1.v:174: //pragma protect key_keyname=CDS_KEY
verilog/inc1.v:175: //pragma protect key_method=RC5
verilog/inc1.v:176: //pragma protect key_block
verilog/inc1.v:177: zzZzZ/4ZzzZZZzzz4zZzZzZZZZzZzZ/Zz+33zZ2zz/zzzzzzzzZZZzZ4z+ZZZZz1
verilog/inc1.v:178: Z1ZzzzZZzZZzz9ZZZZ37zzZzZzZzzz9ZZzzZzZz9Zz64+z8Z7ZzZZZzzzzZZZzZz
verilog/inc1.v:179: zzZzZZZzZ0463zzzzzZzZ6z00z4zZzzZZzzZzzzZZ8zzz09ZzZZZZZ==
verilog/inc1.v:180: //pragma protect end_key_block
verilog/inc1.v:181: //pragma protect digest_block
verilog/inc1.v:182: ZzZZzzZ9ZZZZz2ZzzzZz/Zzzz8Z=
verilog/inc1.v:183: //pragma protect end_digest_block
verilog/inc1.v:184: //pragma protect data_block
verilog/inc1.v:185: ZZZ8zZzz6ZZ/zZZ5zZZzzz3ZzzzZzZZZ6ZzZzZZZZZz1zzZZZZ7ZZZZz3Zzz+9zz
verilog/inc1.v:186: 4zzz+8zZzzzzZzZZzzzZzz1Z7ZzZz+zZz8ZZZZzZ6ZzzZzZZzzZZzzZzzZzZzZzZ
verilog/inc1.v:187: ZzzzzZ0zZz1ZzzZzzZzZzz==
verilog/inc1.v:188: //pragma protect end_data_block
verilog/inc1.v:189: //pragma protect digest_block
verilog/inc1.v:190: Z4Z6zZzZ3Z7ZZ6zzZZZZzzzzZZZ=
verilog/inc1.v:191: //pragma protect end_digest_block
verilog/inc1.v:192: //pragma protect end_protected
verilog/inc1.v:193: endmodule
verilog/inc1.v:194:
verilog/inc1.v:195: COMMENT: //======================================================================
verilog/inc1.v:195: /*CMT*/
verilog/inc1.v:196: COMMENT: // macro call with define that has comma
verilog/inc1.v:196: /*CMT*/
verilog/inc1.v:197:
verilog/inc1.v:198:
verilog/inc1.v:199:
verilog/inc1.v:200:
verilog/inc1.v:201:
verilog/inc1.v:202:
verilog/inc1.v:203:
verilog/inc1.v:204:
verilog/inc1.v:205: DS_begin addr <= ((DS_{DS_regs[DS_6], DS_regs[DS_7]} + 1)); rd <= 1; end and DS_begin addr <= ((DS_{DS_regs[DS_6], DS_regs[DS_7]})); wdata <= (rdata); wr <= 1; end
verilog/inc1.v:206: DS_begin addr <= (DS_{DS_regs[DS_6], DS_regs[DS_7]} + 1); rd <= 1; end
verilog/inc1.v:207: DS_begin addr <= (DS_{DS_regs[DS_6], DS_regs[DS_7]}); wdata <= (rdata); wr <= 1; end more
verilog/inc1.v:208:
verilog/inc1.v:209: COMMENT: //======================================================================
verilog/inc1.v:209: /*CMT*/
verilog/inc1.v:210: COMMENT: // include of parameterized file
verilog/inc1.v:210: /*CMT*/
verilog/inc1.v:211:
verilog/inc1.v:212:
verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0
verilog/inc1.v:212: `line 1 "verilog/t_preproc_inc4.vh" 1
verilog/t_preproc_inc4.vh:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/t_preproc_inc4.vh:1: /*CMT*/
verilog/t_preproc_inc4.vh:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0
verilog/t_preproc_inc4.vh:2: /*CMT*/
verilog/t_preproc_inc4.vh:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/t_preproc_inc4.vh:3: /*CMT*/
verilog/t_preproc_inc4.vh:4:
verilog/t_preproc_inc4.vh:5:
verilog/t_preproc_inc4.vh:6:
verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2
verilog/inc1.v:212: `line 212 "verilog/inc1.v" 0
verilog/inc1.v:212:
verilog/inc1.v:213:
verilog/inc1.v:214:
verilog/inc1.v:215:
verilog/inc1.v:216:
verilog/inc1.v:217:
verilog/inc1.v:218:
verilog/inc1.v:219:
verilog/inc1.v:220:
verilog/inc1.v:221:
verilog/inc1.v:222: COMMENT: //======================================================================
verilog/inc1.v:222: /*CMT*/
verilog/inc1.v:223: COMMENT: // macro call with , in {}
verilog/inc1.v:223: /*CMT*/
verilog/inc1.v:224:
verilog/inc1.v:225:
verilog/inc1.v:226: DS_$blah("ab,cd","e,f");
verilog/inc1.v:227: DS_$blah(this.logfile,vec);
verilog/inc1.v:228: DS_$blah(this.logfile,vec[1,2,3]);
verilog/inc1.v:229: DS_$blah(this.logfile,{blah.name(), " is not foo"});
verilog/inc1.v:230:
verilog/inc1.v:231: COMMENT: //======================================================================
verilog/inc1.v:231: /*CMT*/
verilog/inc1.v:232: COMMENT: // pragma/default net type
verilog/inc1.v:232: /*CMT*/
verilog/inc1.v:233:
verilog/inc1.v:234: `pragma foo = 1
verilog/inc1.v:235: `default_nettype none
verilog/inc1.v:236: `default_nettype uwire
verilog/inc1.v:237:
verilog/inc1.v:238: COMMENT: //======================================================================
verilog/inc1.v:238: /*CMT*/
verilog/inc1.v:239: COMMENT: // Ifdef
verilog/inc1.v:239: /*CMT*/
verilog/inc1.v:240:
verilog/inc1.v:241:
verilog/inc1.v:242:
verilog/inc1.v:243:
verilog/inc1.v:244:
verilog/inc1.v:245: Line_Preproc_Check 245
verilog/inc1.v:246:
verilog/inc1.v:247: COMMENT: //======================================================================
verilog/inc1.v:247: /*CMT*/
verilog/inc1.v:248: COMMENT: // bug84
verilog/inc1.v:248: /*CMT*/
verilog/inc1.v:249:
verilog/inc1.v:250: COMMENT: // Hello, comments MIGHT not be legal
verilog/inc1.v:250: COMMENT: /*more,,)cmts*/
verilog/inc1.v:251: COMMENT: // But newlines ARE legal... who speced THAT?
verilog/inc1.v:252: /*CMT*/ /*CMT*/ /*CMT*/
verilog/inc1.v:252:
verilog/inc1.v:252:
verilog/inc1.v:253: DS_(p,q)
verilog/inc1.v:254: COMMENT: //Here
verilog/inc1.v:254:
verilog/inc1.v:255:
verilog/inc1.v:256: COMMENT: //Too
verilog/inc1.v:256:
verilog/inc1.v:257: COMMENT: /*CMT*/
verilog/inc1.v:257: COMMENT: /*CMT*/
verilog/inc1.v:257: DS_( /*CMT*/ x,y /*CMT*/ )
verilog/inc1.v:258: Line_Preproc_Check 258
verilog/inc1.v:259:
verilog/inc1.v:260: COMMENT: //======================================================================
verilog/inc1.v:260: /*CMT*/
verilog/inc1.v:261: COMMENT: // defines split arguments
verilog/inc1.v:261: /*CMT*/
verilog/inc1.v:262:
verilog/inc1.v:263:
verilog/inc1.v:264:
verilog/inc1.v:265:
verilog/inc1.v:266:
verilog/inc1.v:267: COMMENT: // 2001 spec doesn't require two tokens, so "beginend" ok
verilog/inc1.v:267: DS_beginDS_end /*CMT*/
verilog/inc1.v:268: COMMENT: // 2001 spec doesn't require two tokens, so "beginend" ok
verilog/inc1.v:268: DS_DS_beginDS_end /*CMT*/
verilog/inc1.v:269: COMMENT: // No space "beginend"
verilog/inc1.v:269: DS_"DS_beginDS_end" /*CMT*/
verilog/inc1.v:270:
verilog/inc1.v:271: COMMENT: //======================================================================
verilog/inc1.v:271: /*CMT*/
verilog/inc1.v:272: COMMENT: // bug106
verilog/inc1.v:272: /*CMT*/
verilog/inc1.v:273:
verilog/inc1.v:274:
verilog/inc1.v:275: `\esc`def
verilog/inc1.v:276:
verilog/inc1.v:277: Not a \`define
verilog/inc1.v:278:
verilog/inc1.v:279: COMMENT: //======================================================================
verilog/inc1.v:279: /*CMT*/
verilog/inc1.v:280: COMMENT: // misparsed comma in submacro
verilog/inc1.v:280: /*CMT*/
verilog/inc1.v:281:
verilog/inc1.v:282:
verilog/inc1.v:283:
verilog/inc1.v:284:
verilog/inc1.v:285: DS_DS_x,y)--DS_bee submacro has comma paren
verilog/inc1.v:286:
verilog/inc1.v:287: COMMENT: //======================================================================
verilog/inc1.v:287: /*CMT*/
verilog/inc1.v:288: COMMENT: // bug191
verilog/inc1.v:288: /*CMT*/
verilog/inc1.v:289:
verilog/inc1.v:290: DS_$display("10 %d %d", $bits(foo), 10);
verilog/inc1.v:291:
verilog/inc1.v:292: COMMENT: //======================================================================
verilog/inc1.v:292: /*CMT*/
verilog/inc1.v:293: COMMENT: // 1800-2009
verilog/inc1.v:293: /*CMT*/
verilog/inc1.v:294:
verilog/inc1.v:295:
verilog/inc1.v:296:
verilog/inc1.v:297:
verilog/inc1.v:298:
verilog/inc1.v:299:
verilog/inc1.v:300: COMMENT: //======================================================================
verilog/inc1.v:300: /*CMT*/
verilog/inc1.v:301: COMMENT: // bug202
verilog/inc1.v:301: /*CMT*/
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:302:
verilog/inc1.v:313:
verilog/inc1.v:314: DS_
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314: assign a3 = ~b3 ;
verilog/inc1.v:314: `line 314 "verilog/inc1.v" 0
verilog/inc1.v:314:
verilog/inc1.v:315:
verilog/inc1.v:316: COMMENT: /* multi \
line1*/
verilog/inc1.v:316:
verilog/inc1.v:316: `line 316 "verilog/inc1.v" 0
verilog/inc1.v:317: /*CMT*/ \
verilog/inc1.v:318:
verilog/inc1.v:318: COMMENT: /*multi \
line2*/
verilog/inc1.v:318:
verilog/inc1.v:318: `line 318 "verilog/inc1.v" 0
verilog/inc1.v:320: /*CMT*/
verilog/inc1.v:320:
verilog/inc1.v:320:
verilog/inc1.v:320:
verilog/inc1.v:320:
verilog/inc1.v:320:
verilog/inc1.v:325:
verilog/inc1.v:325: DS_
verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0
verilog/inc1.v:325: COMMENT: /* multi
line 3*/
verilog/inc1.v:325:
verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0
verilog/inc1.v:325: /*CMT*/
verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0
verilog/inc1.v:325: def i
verilog/inc1.v:325: `line 325 "verilog/inc1.v" 0
verilog/inc1.v:325:
verilog/inc1.v:326:
verilog/inc1.v:327: COMMENT: //======================================================================
verilog/inc1.v:327: /*CMT*/
verilog/inc1.v:328:
verilog/inc1.v:329: COMMENT: // verilator NOT IN DEFINE
verilog/inc1.v:329:
verilog/inc1.v:330:
verilog/inc1.v:331: COMMENT: /* verilator NOT PART
OF DEFINE */
verilog/inc1.v:331:
verilog/inc1.v:332:
verilog/inc1.v:333:
verilog/inc1.v:333:
verilog/inc1.v:335: COMMENT: // CMT NOT
verilog/inc1.v:337:
verilog/inc1.v:337:
verilog/inc1.v:337:
verilog/inc1.v:338:
verilog/inc1.v:339: COMMENT: /*CMT*/
verilog/inc1.v:339: 1 DS_ /*CMT*/ (nodef)
verilog/inc1.v:340: COMMENT: /* verilator PART OF DEFINE */
verilog/inc1.v:340: 2 DS_ /*CMT*/ (hasdef)
verilog/inc1.v:341: COMMENT: /*CMT*/
verilog/inc1.v:341: 3 DS_ /*CMT*/ (nodef)
verilog/inc1.v:342: COMMENT: /* verilator PART
OF DEFINE */
verilog/inc1.v:342: 4 DS_
verilog/inc1.v:342: `line 342 "verilog/inc1.v" 0
verilog/inc1.v:342: /*CMT*/ (nodef)
verilog/inc1.v:343: 5 DS_also in
verilog/inc1.v:343: `line 343 "verilog/inc1.v" 0
verilog/inc1.v:343: COMMENT: /*CMT*/
verilog/inc1.v:343: also3 /*CMT*/ (nodef)
verilog/inc1.v:344:
verilog/inc1.v:344:
verilog/inc1.v:346: DS_HAS a NEW
verilog/inc1.v:346: `line 346 "verilog/inc1.v" 0
verilog/inc1.v:346: LINE
verilog/inc1.v:347:
verilog/inc1.v:348: COMMENT: //======================================================================
verilog/inc1.v:348: /*CMT*/
verilog/inc1.v:349:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:350:
verilog/inc1.v:362:
verilog/inc1.v:363:
verilog/inc1.v:364:
verilog/inc1.v:365:
verilog/inc1.v:366: EXP: clxx_scen
verilog/inc1.v:367: DS_clxx_scen
verilog/inc1.v:368: EXP: clxx_scen
verilog/inc1.v:369: DS_"DS_clxx_scen"
verilog/inc1.v:370:
verilog/inc1.v:371: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
verilog/inc1.v:372: DS_DS_
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: do
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: COMMENT: /* synopsys translate_off */
verilog/inc1.v:372: /*CMT*/
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372:
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372:
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372:
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: if (start("verilog/inc1.v", 372)) begin
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372:
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: message({"Blah-", DS_"DS_clx_scen", " end"});
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: end
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: COMMENT: /* synopsys translate_on */
verilog/inc1.v:372: /*CMT*/
verilog/inc1.v:372: `line 372 "verilog/inc1.v" 0
verilog/inc1.v:372: while(0);
verilog/inc1.v:373:
verilog/inc1.v:374: COMMENT: //======================================================================
verilog/inc1.v:374: /*CMT*/
verilog/inc1.v:375:
verilog/inc1.v:376:
verilog/inc1.v:376:
verilog/inc1.v:376:
verilog/inc1.v:376:
verilog/inc1.v:380: DS_
verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0
verilog/inc1.v:380:
verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0
verilog/inc1.v:380:
verilog/inc1.v:380: `line 380 "verilog/inc1.v" 0
verilog/inc1.v:380:
verilog/inc1.v:381:
verilog/inc1.v:382: COMMENT: //`ifndef def_fooed_2 `error "No def_fooed_2" `endif
verilog/inc1.v:382: /*CMT*/
verilog/inc1.v:383: EXP: This is fooed
verilog/inc1.v:384: DS_This is fooed
verilog/inc1.v:385: EXP: This is fooed_2
verilog/inc1.v:386: DS_This is fooed_2
verilog/inc1.v:387:
verilog/inc1.v:388: COMMENT: //======================================================================
verilog/inc1.v:388: /*CMT*/
verilog/inc1.v:389:
verilog/inc1.v:390: DS_np
verilog/inc1.v:391: DS_np
verilog/inc1.v:392: COMMENT: //======================================================================
verilog/inc1.v:392: /*CMT*/
verilog/inc1.v:393: COMMENT: // It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution?
verilog/inc1.v:393: /*CMT*/
verilog/inc1.v:394:
verilog/inc1.v:395:
verilog/inc1.v:396:
verilog/inc1.v:397:
verilog/inc1.v:398:
verilog/inc1.v:399:
verilog/inc1.v:400:
verilog/inc1.v:401:
verilog/inc1.v:402: COMMENT: //======================================================================
verilog/inc1.v:402: /*CMT*/
verilog/inc1.v:403: COMMENT: // Metaprogramming
verilog/inc1.v:403: /*CMT*/
verilog/inc1.v:404:
verilog/inc1.v:405:
verilog/inc1.v:406:
verilog/inc1.v:407:
verilog/inc1.v:408:
verilog/inc1.v:409:
verilog/inc1.v:410:
verilog/inc1.v:411:
verilog/inc1.v:412:
verilog/inc1.v:413:
verilog/inc1.v:414: DS_DS_DS_DS_DS_hello3hello3hello3
verilog/inc1.v:415: DS_DS_DS_DS_DS_hello4hello4hello4hello4
verilog/inc1.v:416: COMMENT: //======================================================================
verilog/inc1.v:416: /*CMT*/
verilog/inc1.v:417: COMMENT: // Include from stringification
verilog/inc1.v:417: /*CMT*/
verilog/inc1.v:418:
verilog/inc1.v:419:
verilog/inc1.v:420:
verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0
verilog/inc1.v:420: `line 1 "verilog/t_preproc_inc4.vh" 1
verilog/t_preproc_inc4.vh:1: COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/t_preproc_inc4.vh:1: /*CMT*/
verilog/t_preproc_inc4.vh:2: COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0
verilog/t_preproc_inc4.vh:2: /*CMT*/
verilog/t_preproc_inc4.vh:3: COMMENT: // without warranty, 2000-2012 by Wilson Snyder.
verilog/t_preproc_inc4.vh:3: /*CMT*/
verilog/t_preproc_inc4.vh:4:
verilog/t_preproc_inc4.vh:5:
verilog/t_preproc_inc4.vh:6:
verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2
verilog/inc1.v:420: `line 420 "verilog/inc1.v" 0
verilog/inc1.v:420:
verilog/inc1.v:421:
verilog/inc1.v:422: COMMENT: //======================================================================
verilog/inc1.v:422: /*CMT*/
verilog/inc1.v:423: COMMENT: // Defines doing defines
verilog/inc1.v:423: /*CMT*/
verilog/inc1.v:424: COMMENT: // Note the newline on the end - required to form the end of a define
verilog/inc1.v:424: /*CMT*/
verilog/inc1.v:425:
verilog/inc1.v:425:
verilog/inc1.v:427:
verilog/inc1.v:428:
verilog/inc1.v:429: DS_ DS_
verilog/inc1.v:429: `line 429 "verilog/inc1.v" 0
verilog/inc1.v:429:
verilog/inc1.v:430:
verilog/inc1.v:431: DS_
verilog/inc1.v:432:
verilog/inc1.v:433: Line_Preproc_Check 433
verilog/inc1.v:434: COMMENT: //======================================================================
verilog/inc1.v:434: /*CMT*/
verilog/inc1.v:435: COMMENT: // Quoted multiline - track line numbers, and insure \\n gets propagated
verilog/inc1.v:435: /*CMT*/
verilog/inc1.v:436:
verilog/inc1.v:436:
verilog/inc1.v:438:
verilog/inc1.v:439: Line_Preproc_Check 439
verilog/inc1.v:441:
verilog/inc1.v:441: DS_DS_"FOO \
verilog/inc1.v:441: BAR " "arg_line1 \
verilog/inc1.v:441: arg_line2" DS_"FOO \
verilog/inc1.v:441: BAR "
verilog/inc1.v:442: `line 442 "verilog/inc1.v" 0
verilog/inc1.v:442: Line_Preproc_Check 442
verilog/inc1.v:443: COMMENT: //======================================================================
verilog/inc1.v:443: /*CMT*/
verilog/inc1.v:444: COMMENT: // bug283
verilog/inc1.v:444: /*CMT*/
verilog/inc1.v:445:
verilog/inc1.v:446:
verilog/inc1.v:447:
verilog/inc1.v:448:
verilog/inc1.v:449: COMMENT: // EXP: abc
verilog/inc1.v:449: /*CMT*/
verilog/inc1.v:450:
verilog/inc1.v:451: DS_DS_abDS_c
verilog/inc1.v:452:
verilog/inc1.v:453:
verilog/inc1.v:454:
verilog/inc1.v:455:
verilog/inc1.v:456:
verilog/inc1.v:457:
verilog/inc1.v:458:
verilog/inc1.v:459: EXP: sonet_frame
verilog/inc1.v:460: DS_DS_DS_sonet_frame
verilog/inc1.v:461: COMMENT: //
verilog/inc1.v:461: /*CMT*/
verilog/inc1.v:462:
verilog/inc1.v:463:
verilog/inc1.v:464: EXP: sonet_frame
verilog/inc1.v:465: DS_DS_sonet_DS_frame
verilog/inc1.v:466: COMMENT: // This result varies between simulators
verilog/inc1.v:466: /*CMT*/
verilog/inc1.v:467:
verilog/inc1.v:468:
verilog/inc1.v:469: EXP: sonet_frame
verilog/inc1.v:470: DS_DS_sonet_frame
verilog/inc1.v:471:
verilog/inc1.v:472: COMMENT: // The existance of non-existance of a base define can make a difference
verilog/inc1.v:472: /*CMT*/
verilog/inc1.v:473:
verilog/inc1.v:474:
verilog/inc1.v:475: EXP: module zzz ; endmodule
verilog/inc1.v:476: module DS_DS_zzz ; endmodule
verilog/inc1.v:477: module DS_DS_zzz ; endmodule
verilog/inc1.v:478:
verilog/inc1.v:479:
verilog/inc1.v:480: EXP: module a_b ; endmodule
verilog/inc1.v:481: module DS_DS_a_b ; endmodule
verilog/inc1.v:482: module DS_DS_a_b ; endmodule
verilog/inc1.v:483:
verilog/inc1.v:484: COMMENT: //======================================================================
verilog/inc1.v:484: /*CMT*/
verilog/inc1.v:485: COMMENT: // bug311
verilog/inc1.v:485: /*CMT*/
verilog/inc1.v:486: COMMENT: /*NEED_SPACE*/
verilog/inc1.v:486: integer /*CMT*/ foo;
verilog/inc1.v:487: COMMENT: //======================================================================
verilog/inc1.v:487: /*CMT*/
verilog/inc1.v:488: synth_test:
verilog/inc1.v:489: COMMENT: // synopsys translate_off
verilog/inc1.v:489: /*CMT*/
verilog/inc1.v:490: synthesis_turned_off
verilog/inc1.v:491: COMMENT: // synthesis translate_on
verilog/inc1.v:491: /*CMT*/
verilog/inc1.v:492: EXP: on
verilog/inc1.v:493: COMMENT: //======================================================================
verilog/inc1.v:493: /*CMT*/
verilog/inc1.v:494: COMMENT: // bug441
verilog/inc1.v:494: /*CMT*/
verilog/inc1.v:495: module t;
verilog/inc1.v:496: COMMENT: //-----
verilog/inc1.v:496: /*CMT*/
verilog/inc1.v:497: COMMENT: // case provided
verilog/inc1.v:497: /*CMT*/
verilog/inc1.v:498: COMMENT: // note this does NOT escape as suggested in the mail
verilog/inc1.v:498: /*CMT*/
verilog/inc1.v:499:
verilog/inc1.v:500:
verilog/inc1.v:500:
verilog/inc1.v:502: initial begin : DS_\`LEX_CAT(a[0],_assignment)
verilog/inc1.v:502: `line 502 "verilog/inc1.v" 0
verilog/inc1.v:502: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end
verilog/inc1.v:503: COMMENT: //-----
verilog/inc1.v:503: /*CMT*/
verilog/inc1.v:504: COMMENT: // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from
verilog/inc1.v:504: /*CMT*/
verilog/inc1.v:505: COMMENT: // substituting and the \ staying in the expansion
verilog/inc1.v:505: /*CMT*/
verilog/inc1.v:506: COMMENT: // Note space after name is important so when substitute it has ending whitespace
verilog/inc1.v:506: /*CMT*/
verilog/inc1.v:507:
verilog/inc1.v:507:
verilog/inc1.v:509: initial begin : DS_\a[0]_assignment_a[1]
verilog/inc1.v:509: `line 509 "verilog/inc1.v" 0
verilog/inc1.v:509: $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end
verilog/inc1.v:510:
verilog/inc1.v:511: COMMENT: //-----
verilog/inc1.v:511: /*CMT*/
verilog/inc1.v:512:
verilog/inc1.v:513:
verilog/inc1.v:514: COMMENT: // RULE: Ignoring backslash does NOT allow an additional expansion level
verilog/inc1.v:514: /*CMT*/
verilog/inc1.v:515: COMMENT: // (Because ESC gets expanded then the \ has it's normal escape meaning)
verilog/inc1.v:515: /*CMT*/
verilog/inc1.v:516: initial begin : DS_\`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end
verilog/inc1.v:517:
verilog/inc1.v:518: COMMENT: //-----
verilog/inc1.v:518: /*CMT*/
verilog/inc1.v:519:
verilog/inc1.v:520:
verilog/inc1.v:520:
verilog/inc1.v:522: COMMENT: // Similar to above; \ does not allow expansion after substitution
verilog/inc1.v:522: /*CMT*/
verilog/inc1.v:523: initial begin : DS_\`CAT(ff,bb)
verilog/inc1.v:523: `line 523 "verilog/inc1.v" 0
verilog/inc1.v:523: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end
verilog/inc1.v:524:
verilog/inc1.v:525: COMMENT: //-----
verilog/inc1.v:525: /*CMT*/
verilog/inc1.v:526:
verilog/inc1.v:526:
verilog/inc1.v:528: COMMENT: // MUST: Unknown macro with backslash escape stays as escaped symbol name
verilog/inc1.v:528: /*CMT*/
verilog/inc1.v:529: initial begin : DS_\`zzz
verilog/inc1.v:529: `line 529 "verilog/inc1.v" 0
verilog/inc1.v:529: $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end
verilog/inc1.v:530:
verilog/inc1.v:531: COMMENT: //-----
verilog/inc1.v:531: /*CMT*/
verilog/inc1.v:532:
verilog/inc1.v:533:
verilog/inc1.v:533:
verilog/inc1.v:535: COMMENT: // SHOULD(simulator-dependant): Known macro with backslash escape expands
verilog/inc1.v:535: /*CMT*/
verilog/inc1.v:536: initial begin : DS_\`FOO
verilog/inc1.v:536: `line 536 "verilog/inc1.v" 0
verilog/inc1.v:536: $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end
verilog/inc1.v:537: COMMENT: // SHOULD(simulator-dependant): Prefix breaks the above
verilog/inc1.v:537: /*CMT*/
verilog/inc1.v:538: initial begin : DS_\xx`FOO
verilog/inc1.v:538: `line 538 "verilog/inc1.v" 0
verilog/inc1.v:538: $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end
verilog/inc1.v:539:
verilog/inc1.v:540: COMMENT: //-----
verilog/inc1.v:540: /*CMT*/
verilog/inc1.v:541: COMMENT: // MUST: Unknown macro not under call with backslash escape doesn't expand
verilog/inc1.v:541: /*CMT*/
verilog/inc1.v:542:
verilog/inc1.v:543: initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end
verilog/inc1.v:544: COMMENT: //-----
verilog/inc1.v:544: /*CMT*/
verilog/inc1.v:545: COMMENT: // MUST: Unknown macro not under call doesn't expand
verilog/inc1.v:545: /*CMT*/
verilog/inc1.v:546:
verilog/inc1.v:547: initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end
verilog/inc1.v:548:
verilog/inc1.v:549: COMMENT: //-----
verilog/inc1.v:549: /*CMT*/
verilog/inc1.v:550: COMMENT: // bug441 derivative
verilog/inc1.v:550: /*CMT*/
verilog/inc1.v:551: COMMENT: // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above)
verilog/inc1.v:551: /*CMT*/
verilog/inc1.v:552:
verilog/inc1.v:553: initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
verilog/inc1.v:554:
verilog/inc1.v:555: COMMENT: //-----
verilog/inc1.v:555: /*CMT*/
verilog/inc1.v:556: COMMENT: // RULE: Because there are quotes after substituting STR, the `A does NOT expand
verilog/inc1.v:556: /*CMT*/
verilog/inc1.v:557:
verilog/inc1.v:558:
verilog/inc1.v:559: initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
verilog/inc1.v:560:
verilog/inc1.v:561: COMMENT: //----
verilog/inc1.v:561: /*CMT*/
verilog/inc1.v:562: COMMENT: // bug845
verilog/inc1.v:562: /*CMT*/
verilog/inc1.v:563:
verilog/inc1.v:564: initial $write("Slashed=`%s'\n", "1//2.3");
verilog/inc1.v:565: COMMENT: //----
verilog/inc1.v:565: /*CMT*/
verilog/inc1.v:566: COMMENT: // bug915
verilog/inc1.v:566: /*CMT*/
verilog/inc1.v:567:
verilog/inc1.v:567:
verilog/inc1.v:569: initial DS_
verilog/inc1.v:569: `line 569 "verilog/inc1.v" 0
verilog/inc1.v:569: $display("%s%s","a1","b2c3\n");
verilog/inc1.v:570: endmodule
verilog/inc1.v:571:
verilog/inc1.v:572: COMMENT: //======================================================================
verilog/inc1.v:572: /*CMT*/
verilog/inc1.v:573: COMMENT: //bug1225
verilog/inc1.v:573: /*CMT*/
verilog/inc1.v:574:
verilog/inc1.v:575:
verilog/inc1.v:576:
verilog/inc1.v:577: $display(DS_DS_"RAM0");
verilog/inc1.v:578: $display(DS_DS_"CPU");
verilog/inc1.v:579:
verilog/inc1.v:580:
verilog/inc1.v:581:
verilog/inc1.v:582:
verilog/inc1.v:583:
verilog/inc1.v:584:
verilog/inc1.v:585:
verilog/inc1.v:586: XXE_FAMILY = DS_XXE_DS_
verilog/inc1.v:587:
verilog/inc1.v:588:
verilog/inc1.v:589:
verilog/inc1.v:590:
verilog/inc1.v:591:
verilog/inc1.v:592:
verilog/inc1.v:593: XYE_FAMILY = DS_XYE_DS_
verilog/inc1.v:594:
verilog/inc1.v:595:
verilog/inc1.v:596:
verilog/inc1.v:597:
verilog/inc1.v:598:
verilog/inc1.v:599:
verilog/inc1.v:600: XXS_FAMILY = DS_XXS_DS_some
verilog/inc1.v:601:
verilog/inc1.v:602:
verilog/inc1.v:603:
verilog/inc1.v:604:
verilog/inc1.v:605:
verilog/inc1.v:606:
verilog/inc1.v:607: XYS_FAMILY = DS_XYS_DS_foo
verilog/inc1.v:608:
verilog/inc1.v:609:
verilog/inc1.v:610:
verilog/inc1.v:611:
verilog/inc1.v:612:
verilog/inc1.v:613: COMMENT: //====
verilog/inc1.v:613: /*CMT*/
verilog/inc1.v:614:
verilog/inc1.v:615:
verilog/inc1.v:616:
verilog/inc1.v:617:
verilog/inc1.v:618:
verilog/inc1.v:619:
verilog/inc1.v:620:
verilog/inc1.v:621:
verilog/inc1.v:622:
verilog/inc1.v:623:
verilog/inc1.v:624:
verilog/inc1.v:625:
verilog/inc1.v:626:
verilog/inc1.v:627:
verilog/inc1.v:628:
verilog/inc1.v:629:
verilog/inc1.v:630:
verilog/inc1.v:631:
verilog/inc1.v:632:
verilog/inc1.v:633:
verilog/inc1.v:634:
verilog/inc1.v:635:
verilog/inc1.v:636:
verilog/inc1.v:637:
verilog/inc1.v:638:
verilog/inc1.v:639:
verilog/inc1.v:640:
verilog/inc1.v:641:
verilog/inc1.v:642:
verilog/inc1.v:643:
verilog/inc1.v:644:
verilog/inc1.v:645:
verilog/inc1.v:646: COMMENT: // NEVER
verilog/inc1.v:646: /*CMT*/
verilog/inc1.v:647:
verilog/inc1.v:648: COMMENT: //bug1227
verilog/inc1.v:648: /*CMT*/
verilog/inc1.v:649:
verilog/inc1.v:650: DS_(.mySig (myInterface.pa5),
verilog/inc1.v:651:
verilog/inc1.v:652: COMMENT: //======================================================================
verilog/inc1.v:652: /*CMT*/
verilog/inc1.v:653: COMMENT: // Stringify bug
verilog/inc1.v:653: /*CMT*/
verilog/inc1.v:654:
verilog/inc1.v:655:
verilog/inc1.v:656: DS_`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
verilog/inc1.v:657:
verilog/inc1.v:658:
verilog/inc1.v:659:
verilog/inc1.v:659:
verilog/inc1.v:661:
verilog/inc1.v:661:
verilog/inc1.v:661:
verilog/inc1.v:661:
verilog/inc1.v:665:
verilog/inc1.v:666: module pcc2_cfg;
verilog/inc1.v:667: generate
verilog/inc1.v:668: DS_
verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0
verilog/inc1.v:668: covergroup a @(posedge b);
verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0
verilog/inc1.v:668: c: coverpoint d iff ((c) === 1'b1); endgroup
verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0
verilog/inc1.v:668: a u_a; DS_
verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0
verilog/inc1.v:668: initial do begin DS_$display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
verilog/inc1.v:669: endgenerate
verilog/inc1.v:670: endmodule
verilog/inc1.v:671:
verilog/inc1.v:672: COMMENT: //======================================================================
verilog/inc1.v:672: /*CMT*/
verilog/inc1.v:673: COMMENT: // Verilog-Perl bug1668
verilog/inc1.v:673: /*CMT*/
verilog/inc1.v:674:
verilog/inc1.v:675: DS_"`NOT_DEFINED_STR"
verilog/inc1.v:676:
verilog/inc1.v:677: COMMENT: //======================================================================
verilog/inc1.v:677: /*CMT*/
verilog/inc1.v:678: COMMENT: // IEEE mandated predefines
verilog/inc1.v:678: /*CMT*/
verilog/inc1.v:679: COMMENT: // undefineall should have no effect on these
verilog/inc1.v:679: /*CMT*/
verilog/inc1.v:680: predef DS_0 0
verilog/inc1.v:681: predef DS_1 1
verilog/inc1.v:682: predef DS_2 2
verilog/inc1.v:683: predef DS_3 3
verilog/inc1.v:684: predef DS_10 10
verilog/inc1.v:685: predef DS_11 11
verilog/inc1.v:686: predef DS_20 20
verilog/inc1.v:687: predef DS_21 21
verilog/inc1.v:688: predef DS_22 22
verilog/inc1.v:689: predef DS_23 23
verilog/inc1.v:690: predef DS_-2 -2
verilog/inc1.v:691: predef DS_-1 -1
verilog/inc1.v:692: predef DS_0 0
verilog/inc1.v:693: predef DS_1 1
verilog/inc1.v:694: predef DS_2 2
verilog/inc1.v:695:
verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2