NAME

Verilog::SigParser - Signal Parsing for Verilog language files

SYNOPSIS

use Verilog::SigParser;

my $parser = new Verilog::SigParser;
$string = $parser->unreadback ();
$line   = $parser->line ();
$parser->parse_preproc_file ($pp);

DESCRIPTION

Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. For a higher level interface to this package, see Verilog::Netlist.

The external interface to Verilog::SigParser is described in the Verilog::Parser module. You will probably want to use the preprocessing option of Verilog::Parser with this package.

In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following methods as appropriate:

CALLBACKS

$self->attribute ( $keyword, $text )

Scanned an attribute (future: Verilog-2001) or meta-comment. The parser inspects the first word of each comment line (//key rest to end of line) or comment block (/*key rest */). It calls $self-attribute( prev_keyword, meta_text ) if the first word has a true value in hash $self-metacomment>.

$self->function ( $keyword, $name )

This method is called when a function is defined.

$self->instant ( $module, $cell, $parameters )

This method is called when a instantiation is defined. The first parameter is the name of the module being instantiated, and the second parameter is the name of the cell. The third is the textual list of parameters, otherwise unparsed.

$self->module ( $keyword, $name, ignored, $in_celldefine )

This method is called when a module is defined.

$self->pin ( $name, $connection, $index )

This method is called when a pin on a instant is defined.

$self->port ( $name )

This method is called when a module port is defined.

$self->ppdefine ( $defvar, $definition )

This method is called when a preprocessor definition is encountered.

$self->signal_decl ( $keyword, $signame, $vector, $mem, $signed )

This method is called when a signal is declared. The first argument, $keyword is ('input', 'output', etc), the second argument is the name of the signal. The third argument is the vector bits or "". The fourth argument is the memory bits or "".

$self->task ( $keyword, $name )

This method is called when a module is defined.

BUGS

This is being distributed as a baseline for future contributions. Don't expect a lot, the Parser is still naive, and there are many awkward cases that aren't covered.

Note the SigParser is focused on extracting signal information. It does NOT extract enough information to derrive general interconnect; for example the contents of 'assign' statements are not parsed.

DISTRIBUTION

Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist, Verilog::Getopt