verilog/inc2.v:1: 
verilog/inc2.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc2.v:1: 
verilog/inc2.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc2.v:1: 
verilog/inc2.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc2.v:1: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc2.v:2: At file verilog/inc2.v  line 2
verilog/inc3.v:1:  
verilog/inc3.v:1: `line 3 "verilog/inc2.v" 0
verilog/inc3.v:1: 
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
inc3_a_filename_from_line_directive:2: // DESCRIPTION: Verilog::Preproc: Example source code
inc3_a_filename_from_line_directive:3: 
inc3_a_filename_from_line_directive:4:  
inc3_a_filename_from_line_directive:5:   
inc3_a_filename_from_line_directive:6:   
inc3_a_filename_from_line_directive:7:   // FOO
inc3_a_filename_from_line_directive:8:   At file inc3_a_filename_from_line_directive  line 8
inc3_a_filename_from_line_directive:9: 
inc3_a_filename_from_line_directive:10:    
inc3_a_filename_from_line_directive:11: 
inc3_a_filename_from_line_directive:11: `line 11 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:11:  // guard
inc3_a_filename_from_line_directive:12: 
inc3_a_filename_from_line_directive:13:  
inc3_a_filename_from_line_directive:14:   
inc3_a_filename_from_line_directive:15: 
inc3_a_filename_from_line_directive:15: `line 15 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:15: 
inc3_a_filename_from_line_directive:16: 
inc3_a_filename_from_line_directive:16: `line 16 "inc3_a_filename_from_line_directive" 2
inc3_a_filename_from_line_directive:16: 
inc3_a_filename_from_line_directive:16: `line 3 "verilog/inc2.v" 0
verilog/inc2.v:3: 
verilog/inc2.v:4:   
verilog/inc2.v:4: `line 4 "verilog/inc2.v" 2
verilog/inc2.v:4: 
verilog/inc2.v:4: `line 1 "verilog/inc1.v" 0
verilog/inc1.v:1: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc1.v:2: text.
verilog/inc1.v:3: 
verilog/inc1.v:4:  /*but not *//* or this either */
verilog/inc1.v:5:  // but not
verilog/inc1.v:6: 
verilog/inc1.v:7:  
verilog/inc1.v:9: 		  
verilog/inc1.v:10: //===========================================================================
verilog/inc1.v:11: 
verilog/inc1.v:12:  
verilog/inc1.v:13: 
verilog/inc1.v:14:  
verilog/inc1.v:15:  
verilog/inc1.v:16: 
verilog/inc1.v:17: /*******COMMENT*****/
verilog/inc1.v:18:  foo  bar 
verilog/inc1.v:19:  foobar2 
verilog/inc1.v:20:   deep   deep  
verilog/inc1.v:21:  first part    		second part 
verilog/inc1.v:22: 
verilog/inc1.v:23: 
verilog/inc1.v:24: