/ 
Module-Build-Xilinx-0.02
River stage zero No dependents
/ Module::Build::Xilinx

NAME

Module::Build::Xilinx - Perl module to generate a Tcl script to create, build and program a Xilinx FPGA development board using Xilinx ISE Webpack.

VERSION

0.02

SYNOPSIS

use strict;
use warnings;
use Module::Build::Xilinx;

my $build = Module::Build::Xilinx->new(
      dist_name => 'fpgasample',
      dist_version => '0.02',
      dist_author => 'Vikas N Kumar <vikas@cpan.org>',
      dist_abstract => 'This is a test',
      proj_params => {
          family => 'spartan3a',
          device => 'xc3s700a',
          package => 'fg484',
          speed => -4,
          language => 'VHDL', # default
      },
      tcl_script => 'program.tcl',
      #... more parameters if necessary ...
);
$build->create_build_script;
# this creates the file Build which when run will create program.tcl

DESCRIPTION

WHAT DOES THE MODULE DO ?

Xilinx ISE Webpack allows for commandline project creation, management, build/compile, run, simulation and programming of the device as well. However, Xilinx ISE Webpack only supports Tcl scripts using their custom xtclsh program.

To ease writing of this Tcl script, this module has been written that adds Perl niceties provided by Module::Build along with some custom requirements for the Xilinx ISE Webpack software.

In version 0.02 of this module, we just generate a Tcl script for the project titled program.tcl which the user has to invoke as follows to continue using it further.

$ xtclsh program.tcl -help

The Tcl script template is generic but we modify it to add the VHDL files that are appropriate for the build that we would like to do.

METHODS

new(%options)

The new() function is similar to Module::Build except for the fact that it supports some extra properties described below.

THE PROPERTIES SUPPORTED

dist_name

The name of the project. This is also available as the property proj_name.

proj_name

The name of the project. Is a read-only property and is set equal to the value of dist_name.

proj_ext

The extension of the Xilinx ISE Webpack project file. By default it is .xise. We have this just in case the extension changes in the future.

proj_params

A hash reference of project parameters necessary to define the development board or the device for which we are creating the build. It has multiple keys defined below:

family

The family of the FPGA such as spartan3a, spartan6 etc. Refer ISE Webpack's documentation for more information.

device

The name of the FPGA chip such as xc3s700a, xc3s1400a etc.

speed

The speed of the FPGA chip as noted in the chip's documentation. The speed can be a negative number. The word 'speed' is a misnomer here but that is what Xilinx uses.

package

The package type of the FPGA chip which is either fg484 or fg400 or fg256 etc.

language

The language supported in the project which as of version 0.02 is VHDL. We do not yet support Verilog.

devboard

The development board that we plan to build for to leverage ISE Webpack's internal files for the board. For example, "Spartan-3A Starter Kit".

tb_toplevel

The top-level name of the entity for the testbench. Default is 'testbench'.

tb_project

The name of the testbench internal project file. Default is 'testbench.prj'.

tb_exe

The name of the testbench executable file that is created. Default is 'testbench.exe'.

tb_lib

The name of the local library that the source files will be considered a part of in the test bench. Default is 'work'. This is used as a namespace reference to the various entities that may be used in the testbench.

tb_cmd

The filename in which commands to the simulator software will be written to. Default is 'simulate.cmd'.

tb_wdb

The testbench debugger file to which data will be written to by the simulation software. Default is 'testbench.wdb'.

tcl_script

The name of the Tcl script to create for the user. Default is 'program.tcl'.

EXPORT

None by default since this is an Object Oriented API.

SEE ALSO

Find me on IRC: #hardware on irc://irc.perl.org as user name vicash.

AUTHOR

Vikas Kumar, <vikas@cpan.org>

COPYRIGHT AND LICENSE

Copyright (C) 2014 by Vikas Kumar

This library is under the MIT license. Please refer the LICENSE file for more information provided with the distribution.